The present invention relates generally to memory devices and more particularly to a memory system for use on a circuit board where the number of loads is minimized.
Memory devices are utilized extensively in printed circuit boards (PCBs). Oftentimes, these memory devices are utilized in both sides of the PCB. To save space on such boards, it is desirable to place these devices on opposite sides of the boards such that they are mirror images of each other.
FIG. 1 illustrates a representative pin assignment of the address pins for a memory device. In this embodiment, the device 10 includes address pins A0-A11. As is seen, address pins A0-A5 are on one side of the device 10 and address pins A11-A6 are on an opposite side of the device. The memory device 10 is preferably a dynamic random access memory (DRAM). For purposes of clarity, only the portions of the memory device relevant to the explanation are described herein. One of ordinary skill in the art readily recognizes that there are other pins such as data pins, power pin and ground pins, and the like that are utilized on the memory device. It is also understood that the particular pin assignment locations are not relevant. The important factor is that memory devices have fixed pin assignments.
Accordingly, if identical memory devices are placed on the opposite sides of the PCB, a pin on one side of the device is opposite its corresponding pin on the other side of the PCB. Typically, to utilize the corresponding pins simultaneously, the corresponding pins are connected by an electrical connection referred to as a via which couples the pin to a driver. In conventional systems, these connections have not created many problems, but as device sizes become smaller and device speeds become faster, these connections look more and more like transmission lines and have the attendant problems associated therewith such as reflections on the lines. Hence, signal integrity techniques must be utilized to ensure these transmission line problems are minimized.
To illustrate this, refer to the following description in conjunction with the accompanying figures. FIGS. 2 and 3 illustrate simplified top front views of the connections of common address pins of two identical DRAMs on opposite sides of a portion of a PCB 12. For the sake of simplicity, it should be understood that these figures are for illustrative purposes only to allow for a straightforward description of this feature. One of ordinary skill in the art recognizes that there are many more pins and many more connections than that shown in these figures.
For ease of understanding, FIG. 2 illustrates the conventional coupling of corresponding pins A0 to A5 connections between two memory devices on the front and back of the portion of the PCB 12, and FIG. 3 illustrates the conventional coupling of corresponding pins A11-A6 between the two memory devices. Hence, in FIG. 2, pins A0-A5, the pins on top of the portion of the PCB 12, are shown on the right hand side of FIG. 2, and their corresponding pins A0xe2x80x2-A5xe2x80x2, the pins on the bottom of the PCB 12, are shown on the left-hand side. Similarly, pins A11-A6 on the top of the portion of the PCB 12 are on the left-hand side of FIG. 3, and pins Axe2x80x211-Axe2x80x26 on the bottom of the portion of the PCB 12 are on the right-hand side. Hence, as is seen, all of the corresponding pins ((A0, Axe2x80x20,) (A1, A1xe2x80x2), etc.) are also opposite each other.
Typically, as is seen in these figures, vias 16a-16f and 16axe2x80x216fxe2x80x2 are utilized to connect the appropriate corresponding pins (A0, A0xe2x80x2) etc. to 20a-20f and 20axe2x80x2-20fxe2x80x2 drive pins. Accordingly, each of pins 20a-20f and 20axe2x80x2-20fxe2x80x2 are utilized to drive two loads (i.e., pins (A0, A0xe2x80x2) etc.).
As before mentioned, as device sizes become smaller and device speeds become higher, these connections look more and more like transmission lines. As a result, signal integrity techniques must be utilized to ensure that transmission line effects are minimized. These signal integrity techniques are complex as well as adding significant expense to the overall system. Since cost is always a factor in integrated circuit design, it is always desirable to minimize costs associated therewith. Therefore, it is readily apparent as the number of pins increase on a memory device, the number of loads increase in a corresponding fashion which is also very undesirable.
Accordingly, what is desired is a system to minimize the number of loads when utilizing multiple memory chips on each side of the board. The system should be straightforward, should not add undue complexity or cost to the system, and be easy to implement on existing architectures. The present invention addresses such a need.
A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other two memory devices such that a first portion coupled to a pin of a second portion forms a coupled load. The coupled load then appears as one load.
Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins. At least a portion of the pins of one of the two memory devices is in close proximity to and coupled to the at least a portion of the pins of the other of the at least two memory devices such that a pin and one memory device is coupled to a pin on the other memory device to form a coupled load. The coupled load then appears as one load. This is accomplished in a preferred embodiment by allowing the pins which are on opposite sides (front and back) of the printed circuit board to be represented as one load and then remapping one of the oppositely disposed pins to have the same functionality as the other oppositely disposed pin.